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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. onet8501pb slls910a ? july 2008 ? revised june 2016 onet8501pb 11.3-gbps rate-selectable limiting amplifier 1 1 features 1 ? up to 11.3-gbps operation ? 2-wire digital interface ? digitally selectable input bandwidth ? adjustable los threshold ? digitally selectable output voltage ? digitally selectable output preemphasis ? adjustable input threshold voltage ? low power consumption ? input offset cancellation ? cml data outputs with on-chip 50- ? back- termination to vcc ? single 3.3-v supply ? output disable ? surface mount small footprint 3-mm 3-mm, 16 ? pin, rohs compliant vqfn package 2 applications ? 10-gigabit ethernet optical receivers ? 2x, 4x, 8x, and 10x fiber channel optical receivers ? sonet oc-192/sdh-64 optical receivers ? sfp+ and xfp transceiver modules ? xenpak, xpak, x2, and 300-pin msa transponder modules ? cable drivers and receivers 3 description the onet8501pb device is a high-speed, 3.3-v limiting amplifier for multiple fiber optic and copper cable applications with data rates from 2 gbps up to 11.3 gbps. the device provides a two-wire serial interface which allows digital control of the bandwidth, output amplitude, output preemphasis, input threshold voltage (slice level), and the loss of signal assert level. predetermined settings for bandwidth and los assert levels can also be selected with external rate selection pins. device information (1) part number package body size (nom) onet8501pb vqfn (16) 3.00 mm 3.00 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. typical application circuit disable vcc din+ din- dout- dout+ los dindin dout- dout+ vccvcc gndgnd onet 8501pb 16 pin qfn c1 0.1 mf c2 0.1 mf c5 330 pf c60.1 mf c4 0.1 mf c3 0.1 mf l1 blm15hd102sn1 coc1 coc2 dis los sda sck rate0 rate1 sda sck rate0 rate1 copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 description (continued) ......................................... 3 6 pin configuration and functions ......................... 3 7 specifications ......................................................... 4 7.1 absolute maximum ratings ...................................... 4 7.2 esd ratings .............................................................. 4 7.3 recommended operating conditions ....................... 4 7.4 dc electrical characteristics .................................... 4 7.5 ac electrical characteristics ..................................... 5 7.6 typical characteristics .............................................. 6 8 detailed description .............................................. 8 8.1 overview ................................................................... 8 8.2 functional block diagram ......................................... 8 8.3 feature description ................................................... 9 8.4 device functional modes .......................................... 9 8.5 programming ........................................................... 11 8.6 register maps ......................................................... 12 9 application and implementation ........................ 18 9.1 application information ............................................ 18 9.2 typical application .................................................. 18 10 power supply recommendations ..................... 20 11 layout ................................................................... 20 11.1 layout guidelines ................................................. 20 11.2 layout example .................................................... 20 12 device and documentation support ................. 21 12.1 receiving notification of documentation updates 21 12.2 community resource ............................................ 21 12.3 trademarks ........................................................... 21 12.4 electrostatic discharge caution ............................ 21 12.5 glossary ................................................................ 21 13 mechanical, packaging, and orderable information ........................................................... 21 4 revision history changes from original (july 2008) to revision a page ? added esd ratings table, feature description section, device functional modes , application and implementation section, power supply recommendations section, layout section, device and documentation support section, and mechanical, packaging, and orderable information section ................................................................................................. 1
3 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 5 description (continued) the onet8501pb provides a gain of about 34 db which ensures a fully differential output swing for input signals as low as 20 mv pp . the output amplitude can be adjusted to 350 mv pp , 650 mv pp , or 850 mv pp . to compensate for frequency-dependent loss of microstrips or striplines connected to the output of the device, programmable preemphasis is included in the output stage. a settable loss of signal detection and output disable are also provided. the device, available in rohs compliant small footprint 3-mm 3-mm, 16-pin vqfn package, typically dissipates less than 170 mw and is characterized for operation from ? 40 c to 100 c. 6 pin configuration and functions rgt package 16-pin vqfn top view pin functions pin type description name no. coc1 5 analog offset cancellation filter capacitor plus terminal. an external capacitor can be connected between this pin and coc2 to reduce the low frequency cutoff. to disable the offset cancellation loop, connect coc1 and coc2 together. coc2 6 analog offset cancellation filter capacitor minus terminal. an external capacitor can be connected between this pin and coc1 to reduce the low frequency cutoff. to disable the offset cancellation loop, connect coc1 and coc2 together. din+ 2 analog-input noninverted data input. differentially 100 ? terminated to din ? . din ? 3 analog-input inverted data input. differentially 100 ? terminated to din+. dis 7 digital-input disables the output stage when set to a high level. dout ? 10 cml-out inverted data output. on-chip 50 ? back-terminated to vcc. dout+ 11 cml-out noninverted data output. on-chip 50 ? back-terminated to vcc. gnd 1,4, ep supply circuit ground. exposed die pad (ep) must be grounded. los 8 open-drain mos high level indicates that the input signal amplitude is below the programmed threshold level. open-drain output. requires an external 10-k ? pullup resistor to vcc for proper operation. rate1 13 digital-input bandwidth selection for noise suppression. rate0 14 digital-input bandwidth selection for noise suppression. sck 15 digital-input serial interface clock input. connect a pullup resistor (10 k ? typical) to vcc. sda 16 digital-input serial interface data input. connect a pullup resistor (10 k ? typical) to vcc. vcc 9, 12 supply 3.3-v 10% supply voltage. not to scale exposed pad 16 sda 5 coc1 1 gnd 12 vcc 15 sck 6 coc2 2 din+ 11 dout+ 14 rate0 7 dis 3 dinC 10 doutC 13 rate1 8 los 4 gnd 9 vcc
4 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. 7 specifications 7.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit v cc supply voltage (2) ? 0.3 4 v v din+ , v din ? voltage at din+, din ? (2) 0.5 4 v v los , v coc1 , v coc2 , v dout+ , v dout ? , v dis , v rate0 , v rate1 , v sda , v sck voltage at los, coc1, coc2, dout+, dout ? , dis, rate0, rate1, sda, sck (2) ? 0.3 4 v v din,diff differential voltage between din+ and din ? 2.5 v i din+ , i din ? , i dout+ , i dout ? continuous current at inputs and outputs 25 ma t lead lead temperature 1.6mm (1/16 inch) from case for 10 s 260 c t a characterized free-air operating temperature ? 40 100 c t j,max maximum junction temperature 125 c t stg storage temperature ? 65 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 7.2 esd ratings value unit v (esd) electrostatic discharge human-body model (hbm), per ansi/esda/jedec js-001 (1) 2000 v charged-device model (cdm), per jedec specification jesd22-c101 (2) 750 7.3 recommended operating conditions min nom max unit v cc supply voltage 2.95 3.3 3.6 v t a operating free-air temperature ? 40 100 c digital input high voltage 2 v digital input low voltage 0.8 v 7.4 dc electrical characteristics over recommended operating conditions, outputs connected to a 50- ? load, amp1 = 0, amp0 = 1 (register 3) unless otherwise noted. typical operating condition is at v cc = 3.3 v and t a = 25 c. parameter test conditions min typ max unit v cc supply voltage 2.95 3.3 3.6 v i vcc supply current dis = 0, cml currents included 50 63 ma r in data input resistance differential 100 ? r out data output resistance single-ended, referenced to v cc 50 ? los high voltage i source = 50 a with 10-k ? pullup to v cc 2.4 v los low voltage i sink = 10 ma with 10-k ? pullup to v cc 0.4 v
5 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated (1) differential return gain given by sdd11, sdd22 = ? 11.6 + 13.33 log 10 (f/8.25), f in ghz 7.5 ac electrical characteristics over recommended operating conditions, outputs connected to a 50- ? load, amp1 = 0, amp0 = 1 (register 3) and maximum bandwidth unless otherwise noted. typical operating condition is at v cc = 3.3 v and t a = 25 c. parameter test condition min typ max unit f 3db-h ? 3-db bandwidth default settings rate1 = 1, rate0 = 0 7.5 9 ghz rate1 = 1, rate0 = 1 8.4 rate1 = 0, rate0 = 1 7.6 rate1 = 0, rate0 = 0 2.4 f 3db-l low frequency ? 3-db bandwidth with 330-pf coc capacitor 10 45 khz v in,min data input sensitivity prbs31 pattern at 11.3 gbps, ber < 10 ? 12 5 9 mv pp v od-min 0.95 v od (output limited) 20 30 prbs31 pattern at 8.5 gbps, ber < 10 ? 12 , rate1 = 1, rate0 = 0 4 prbs31 pattern at 4.25 gbps, ber < 10 ? 12 , rate1 = 1, rate0 = 1 4 prbs31 pattern at 2.125 gbps, ber < 10 ? 12 , rate1 = 0, rate0 = 1 4 sdd11 differential input return gain 0.01 ghz < f < 3.9 ghz ? 16 db 3.9 ghz < f < 12.1 ghz see (1) sdd22 differential output return gain 0.01 ghz < f < 3.9 ghz ? 16 db 3.9 ghz < f < 12.1 ghz see (1) scd11 differential to common-mode conversion gain 0.01 ghz < f < 12.1 ghz ? 15 db scc22 common-mode output return gain 0.01 ghz < f < 7.5 ghz ? 13 db 7.5 ghz < f < 12.1 ghz ? 9 a small signal gain 29 34 db v in,max data input overload 2000 mv pp dj deterministic jitter at 11.3 gbps v in = 15 mv pp , k28.5 pattern 3 8 ps pp v in = 30 mv pp , k28.5 pattern 3 10 v in = 2000 mv pp , k28.5 pattern 6 15 deterministic jitter at 8.5 gbps v in = 30 mv pp , k28.5 pattern, rate1 = 1, rate0 = 0 4 ps pp deterministic jitter at 4.25 gbps v in = 30 mv pp , k28.5 pattern, rate1 = 1, rate0 = 1 6 ps pp deterministic jitter at 2.125 gbps v in = 30 mv pp , k28.5 pattern, rate1 = 0, rate0 = 1 8 ps pp rj random jitter v in = 30 mv pp 1 ps rms v od differential data output voltage v in > 30 mv pp , dis = 0, amp1 = 0, amp0 = 0 250 350 450 mv pp v in > 30 mv pp , dis = 0, amp1 = 0, amp0 = 1 500 650 800 v in > 30 mv pp , dis = 0, amp1 = 1, amp0 = 1 650 850 1050 dis = 1 5 mv rms v preem output preemphasis step size 1 db t r output rise time 20% to 80%, v in > 30 mv pp 28 40 ps t f output fall time 20% to 80%, v in > 30 mv pp 28 40 ps cmov ac common-mode output voltage prbs31 pattern; amp1 = 0, amp0 = 1 7 mv rms v th low los assert threshold range min k28.5 pattern at 11.3 gbps, losrng = 0 15 mv pp low los assert threshold range max k28.5 pattern at 11.3 gbps, losrng = 0 35 v th high los assert threshold range min k28.5 pattern at 11.3 gbps, losrng = 1 35 mv pp high los assert threshold range max k28.5 pattern at 11.3 gbps, losrng = 1 80 los threshold variation versus temperature at 11.3 gbps 1.5 db versus supply voltage v cc at 11.3 gbps 1 versus data rate 1.5 los hysteresis (electrical) k28.5 pattern at 11.3 gbps 2 4 6 db t los_ast los assert time 2.5 10 80 s t los_dea los deassert time 2.5 10 80 s t dis disable response time 20 ns
6 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 7.6 typical characteristics typical operating condition is at v cc = 3.3 v, t a = 25 c, amp1 = 0, amp0 = 1 (register 3), and maximum bandwidth unless otherwise noted. figure 1. frequency response figure 2. bandwidth vs register setting figure 3. transfer function figure 4. differential input return gain vs frequency figure 5. differential output return gain vs frequency figure 6. bit-error ratio vs input voltage (11.3 gbps) -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0.1 1 10 100 sdd11 - db f - frequency - ghz 0 1 2 3 4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 register setting - decimal bandwidth - ghz 0 5 10 15 20 25 30 35 40 45 50 0 1 10 100 f - frequency - ghz sdd21 - db 1e-13 1e-10 1e-07 1e-04 0 1 2 3 4 5 bit-error ratio v - input voltage - mvpp i -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 0.1 1 10 100 sdd22 - db f - frequency - ghz 0 100 200 300 400 500 600 700 800 0 20 40 60 80 100 v - input voltage - mvpp i v - output voltage - mvpp o
7 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated typical characteristics (continued) typical operating condition is at v cc = 3.3 v, t a = 25 c, amp1 = 0, amp0 = 1 (register 3), and maximum bandwidth unless otherwise noted. figure 7. deterministic jitter vs input voltage figure 8. random jitter vs input voltage figure 9. los assert/deassert voltage vs register setting losrng = 0 figure 10. los assert/deassert voltage vs register setting losrng = 1 figure 11. los hysteresis vs register setting losrng = 0 figure 12. los hysteresis vs register setting losrng = 1 0 1 2 3 4 5 6 7 8 128 148 168 188 208 228 248 register setting - decimal los hysteresis - db 0 1 2 3 4 5 6 7 8 158 168 178 188 198 208 218 228 238 248 258 register setting - decimal los hysteresis - db 0 10 20 30 40 50 60 70 80 90 128 148 168 188 208 228 248 register setting - decimal los assert/deassert voltage - mvpp los assert voltage los deassert voltage 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 158 168 178 188 198 208 218 228 238 248 258 register setting - decimal los assert/deassert voltage - mvpp los assert voltage los deassert voltage 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 0 10 20 30 40 50 60 70 80 90 100 random jitter - ps rms v - input voltage - mvpp i 0 1 2 3 4 5 6 7 8 9 10 0 200 400 600 800 1000 1200 1400 1600 1800 2000 v - input voltage - mvpp i deterministic jitter - ps pp
8 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 8 detailed description 8.1 overview this compact, low-power, 11.3-gbps limiting amplifier consists of a high-speed data path with offset cancellation block (dc feedback) combined with an analog settable input threshold adjust, a loss-of-signal detection block using two peak detectors, a two-wire interface with a control-logic block and a band-gap voltage reference and bias current generation block. see functional block diagram for a simplified block diagram of the onet8501pb. 8.2 functional block diagram output buffer gain stage 50 50 vcc 100 settings 4 bit input threshold preemphasis amplitude rsarsb rscrsd losa poweron reset bandgap voltage reference and bias current generation losblosc 2wire interface & control logic sdasck dis din+ din- sda sck dis dout+ dout- gain stage input buffer with selectable bandwidth offset cancellation rate0 rate0 rate1 rate1 4 bit 8 bit register 2 bit 4 bit + select 4 bit + select 4 bit + select 4 bit + select 7 bit + select 7 bit + select 7 bit + select 7 bit + select losd los detection los coc1 coc2 vcc gnd 4 bit selrate 7 bit sellos copyright ? 2016, texas instruments incorporated
9 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 8.3 feature description 8.3.1 high-speed data path the high-speed data signal is applied to the data path by means of input signal pins din+ / din ? . the data path consists of a 100- ? differential termination resistor followed by a digitally controlled bandwidth switch input buffer for rate select. the rate1 and rate0 pins can be used to control the bandwidth of the filter. default bandwidth settings are used; however, these can be changed using registers 4 through 7 through the serial interface. for details regarding the rate selection, see table 19 . a gain stage and an output buffer stage follow the input buffer, which together provide a gain of 34 db. the device can accept input amplitude levels from 5 mv pp up to 2000 mv pp . the amplified data output signal is available at the output pins dout+ and dout, which includes on-chip 2 50- ? back-termination to vcc. offset cancellation compensates for internal offset voltages and thus ensures proper operation even for very small input data signals. the offset cancellation can be disabled so that the input threshold voltage can be adjusted to optimize the bit error rate or change the eye crossing to compensate for input signal pulse width distortion. the offset cancellation can be disabled by setting ocdis = 1 (bit 1 of register 0). the input threshold level can be adjusted using register settings thadj[0..7] (register 1). for details regarding input threshold adjust, see table 19 . the low frequency cutoff is as low as 80 khz with the built-in filter capacitor. for applications, which require even lower cutoff frequencies, an additional external filter capacitor may be connected to the coc1 and coc2 pins. a value of 330 pf results in a low frequency cutoff of 10 khz. 8.3.2 band-gap voltage and bias generation the onet8501pb limiting amplifier is supplied by a single 3.3-v supply voltage connected to the vcc pins. this voltage is referred to ground (gnd). on-chip band-gap voltage circuitry generates a reference voltage, independent of supply voltage, from which all other internally required voltages and bias currents are derived. 8.4 device functional modes 8.4.1 high-speed output buffer the output amplitude of the buffer can be set to 350 mv pp , 650 mv pp , or 850 mv pp using register settings amp[0..1] (register 3) through the serial interface. to compensate for frequency dependant losses of transmission lines connected to the output, the onet8501pb has adjustable preemphasis of the output stage. the preemphasis can be set from 0 to 8 db in 1-db steps using register settings peadj[0..3] (register 2). 8.4.2 rate select there are 16 possible internal filter settings (4 bit) to adjust the small signal bandwidth to the data rate. for fast rate selection, 4 default values can be selected with the rate1 and rate0 pins. using the serial interface, the bandwidth settings can be customized instead of using the default values. the default bandwidths and the registers used to change the bandwidth settings are shown in table 1 . table 1. rate selection default settings and registers used for adjustment rate1 rate0 default bandwidth (ghz) register used for adjustment 0 0 2.4 rsa (register 4) 0 1 7.6 rsb (register 5) 1 1 8.4 rsc (register 6) 1 0 9 rsd (register 7) if the rate select register selection bit is set low, for example rsasel = 0 (bit 7 of register 4), then the default bandwidth for that register is used. if the register selection bit is set high, for example rsasel = 1 (bit 7 of register 4), then the content of rsa[0..3] (register 4) is used to set the input filter bandwidth when rate0 = 0 and rate1 = 0. the settings of the rate selection registers rsa, rsb, rsc, rsd, and the corresponding filter bandwidths are shown in table 2 .
10 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated table 2. available bandwidth settings rsx3 rsx2 rsx1 rsx0 typical bandwidth (ghz) 0 0 0 0 9 0 0 0 1 8.6 0 0 1 0 8.4 0 0 1 1 8.1 0 1 0 0 7.9 0 1 0 1 7.6 0 1 1 0 6.9 0 1 1 1 6.2 1 0 0 0 5.2 1 0 0 1 4.2 1 0 1 0 3.7 1 0 1 1 3.4 1 1 0 0 3.2 1 1 0 1 2.8 1 1 1 0 2.6 1 1 1 1 2.4 the rate1 and rate0 pins do not have to be used if the serial interface is being used. if rate1 is not connected it is internally pulled high and if rate0 is not connected it is internally pulled low, thus selecting register 7. therefore, changing the contents of rsd[0..3] (register 7) through the serial interface can be used to adjust the bandwidth. 8.4.3 loss-of-signal detection the loss of signal detection is done by 2 separate level detectors to cover a wide dynamic range. the peak values of the input signal and the output signal of the gain stage are monitored by the peak detectors. the peak values are compared to a predefined loss of signal threshold voltage inside the loss of signal detection block. as a result of the comparison, the los signal, which indicates that the input signal amplitude is below the defined threshold level, is generated. the los assert level is settable through the serial interface. there are 2 los ranges settable with the losrng bit (bit 2 register 0) through the serial interface. by setting the bit losrng = 1, the high range of the los assert values are used (35 mv pp to 80 mv pp ) and by setting the bit losrng = 0, the low range of the los assert values are used (15 mv pp to 35 mv pp ). there are 128 possible internal los settings (7 bit) for each los range to adjust the los assert level. for fast los selection, 4 default values can be selected with the rate1 and rate0 pins; however, the los settings can be customized instead of using the default values. the default los assert levels and the registers used to change the los settings are shown in table 3 . table 3. los assert level default settings and registers used for adjustment rate1 rate0 default los assert level (mv pp ) register used for adjustment 0 0 15 losa (register 8) 0 1 18 losb (register 9) 1 1 26 losc (register 10) 1 0 26 losd (register 11) if the los register selection bit is set low, for example losasel = 0 (bit 7 of register 8), then the default los assert level for that register is used. if the register selection bit is set high, for example losasel = 1 (bit 7 of register 8), then the content of losa[0..6] (register 8) is used to set the los assert level when rate1 = 0 and rate0 = 0. the rate1 and rate0 pins do not have to be used if the serial interface is being used. if rate1 is not connected it is internally pulled high and if rate0 is not connected it is internally pulled low, thus selecting register 11. therefore, changing the content of losd[0..6] (register 11) through the serial interface can be used to adjust the los assert level.
11 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 8.5 programming 8.5.1 2-wire interface and control logic the onet8501pb uses a 2-wire serial interface for digital control. the two circuit inputs, sda and sck, are driven, respectively, by the serial data and serial clock from a microcontroller, for example. both inputs include 100-k ? pullup resistors to vcc. for driving these inputs, ti recommends an open-drain output. the 2-wire interface allows write access to the internal memory map to modify control registers and read access to read out control and status signals. the onet8501pb is a slave device only which means that it can not initiate a transmission itself; it always relies on the availability of the sck signal for the duration of the transmission. the master device provides the clock signal as well as the start and stop commands. the protocol for a data transmission is as follows: 1. start command 2. 7-bit slave address (1000100) followed by an eighth bit which is the data direction bit (r/w). a zero indicates a write and a 1 indicates a read. 3. 8-bit register address 4. 8-bit register data word 5. stop command regarding timing, the onet8501pb is i 2 c compatible. the typical timing is shown in figure 13 and a complete data transfer is shown in figure 14 . parameters for figure 13 are defined in table 4 . bus idle: both sda and sck lines remain high start data transfer: a change in the state of the sda line, from high to low, while the sck line is high, defines a start condition (s). each data transfer begins with a start condition. stop data transfer: a change in the state of the sda line from low to high while the sck line is high defines a stop condition (p). each data transfer ends with a stop condition; however, if the master still wishes to communicate on the bus, it can generate a repeated start condition and address another slave without first generating a stop condition. data transfer: only one data byte can be transferred between a start and a stop condition. the receiver acknowledges the transfer of data. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge bit. the transmitter releases the sda line and a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge clock pulse. setup and hold times must be taken into account. when a slave-receiver doesn ? t acknowledge the slave address, the data line must be left high by the slave. the master can then generate a stop condition to abort the transfer. if the slave-receiver does acknowledge the slave address but some time later in the transfer cannot receive any more data bytes, the master must abort the transfer. this is indicated by the slave generating the not acknowledge on the first byte to follow. the slave leaves the data line high and the master generates the stop condition. figure 13. i 2 c timing diagram p s s p sdasck t buf t low t r t f t high t hdsta t hdsta t hddat t sudat t susta t susto
12 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated programming (continued) table 4. timing diagram definitions parameter min max unit f sck sck clock frequency 400 khz t buf bus free time between start and stop conditions 1.3 s t hdsta hold time after repeated start condition. after this period, the first clock pulse is generated 0.6 s t low low period of the sck clock 1.3 s t high high period of the sck clock 0.6 s t susta setup time for a repeated start condition 0.6 s t hddat data hold time 0 s t sudat data setup time 100 ns t r rise time of both sda and sck signals 300 ns t f fall time of both sda and sck signals 300 ns t susto setup time for stop condition 0.6 s figure 14. i 2 c data transfer 8.6 register maps the register mapping for read and write register addresses 0 (0x00) through 11 (0x0b) are shown in table 5 through table 16 . the register mapping for the read only register addresses 14 (0x0e) and 15 (0x0f) are shown in table 17 and table 18 . table 19 describes the circuit functionality based on the register settings. 8.6.1 register 0 (0x00) mapping ? control settings table 5. register 0 (0x00) mapping ? control settings register address 0 (0x00) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? dis losrng ocdis i2cdis 8.6.2 register 1 (0x01) mapping ? input threshold adjust table 6. register 1 (0x01) mapping ? input threshold adjust register address 1 (0x01) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 thadj7 thadj6 thadj5 thadj4 thadj3 thadj2 thadj1 thadj0 s sdasck p 1-7 slave address r/w ack 8 9 1-7 8 9 register address ack 1-7 8 9 ack registerfunction
13 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 8.6.3 register 2 (0x02) mapping ? preemphasis adjust table 7. register 2 (0x02) mapping ? preemphasis adjust register address 2 (0x02) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? peadj3 peadj2 peadj1 peadj0 8.6.4 register 3 (0x03) mapping ? output amplitude adjust table 8. register 3 (0x03) mapping ? output amplitude adjust register address 3 (0x03) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? ? ? amp1 amp0 8.6.5 register 4 (0x04) mapping ? rate selection register a table 9. register 4 (0x04) mapping ? rate selection register a register address 4 (0x04) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsasel ? ? ? rsa3 rsa2 rsa1 rsa0 8.6.6 register 5 (0x05) mapping ? rate selection register b table 10. register 5 (0x05) mapping ? rate selection register b register address 5 (0x05) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsbsel ? ? ? rsb3 rsb2 rsb1 rsb0 8.6.7 register 6 (0x06) mapping ? rate selection register c table 11. register 6 (0x06) mapping ? rate selection register c register address 6 (0x06) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rscsel ? ? ? rsc3 rsc2 rsc1 rsc0 8.6.8 register 7 (0x07) mapping ? rate selection register d table 12. register 7 (0x07) mapping ? rate selection register d register address 7 (0x07) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsdsel ? ? ? rsd3 rsd2 rsd1 rsd0 8.6.9 register 8 (0x08) mapping ? los assert level register a table 13. register 8 (0x08) mapping ? los assert level register a register address 8 (0x08) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 losasel losa6 losa5 losa4 losa3 losa2 losa1 losa0
14 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 8.6.10 register 9 (0x09) mapping ? los assert level register b table 14. register 9 (0x09) mapping ? los assert level register b register address 9 (0x09) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 losbsel losb6 losb5 losb4 losb3 losb2 losb1 losb0 8.6.11 register 10 (0x0a) mapping ? los assert level register c table 15. register 10 (0x0a) mapping ? los assert level register c register address 10 (0x0a) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 loscsel losc6 losc5 losc4 losc3 losc2 losc1 losc0 8.6.12 register 11 (0x0b) mapping ? los assert level register d table 16. register 11 (0x0b) mapping ? los assert level register d register address 11 (0x0b) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 losdsel losd6 losd5 losd4 losd3 losd2 losd1 losd0 8.6.13 register 14 (0x0e) mapping ? selected rate setting (read only) table 17. register 14 (0x0e) mapping ? selected rate setting (read only) register address 14 (0x0e) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? ? ? ? selrate3 selrate2 selrate1 selrate0 8.6.14 register 15 (0x0f) mapping ? selected los level (read only) table 18. register 15 (0x0f) mapping ? selected los level (read only) register address 15 (0x0f) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ? sellos6 sellos5 sellos4 sellos3 sellos2 sellos1 sellos0 table 19. register functionality symbol register bit function dis output disable bit 3 output disable bit: 1 = output disabled 0 = output enabled losrng los range bit 2 los range bit: 1 = high los assert voltage range 0 = low los assert voltage range ocdis offset cancellation disable bit 1 offset cancellation disable bit: 1 = offset cancellation is disabled 0 = offset cancellation is enabled i2cdis i 2 c disable bit 0 i 2 c disable bit: 1 = i 2 c is disabled. 0 = i 2 c is enabled. this is the default setting.
15 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated table 19. register functionality (continued) symbol register bit function thadj7 input threshold adjust bit 7 (msb) input threshold adjustment setting: thadj6 input threshold adjust bit 6 maximum positive shift for 00000001 (1) thadj5 input threshold adjust bit 5 minimum positive shift for 01111111 (127) thadj4 input threshold adjust bit 4 zero shift for 10000000 (128) thadj3 input threshold adjust bit 3 minimum negative shift for 10000001 (129) thadj2 input threshold adjust bit 2 maximum negative shift for 11111111 (255) thadj1 input threshold adjust bit 1 thadj0 input threshold adjust bit 0 (lsb) peadj3 preemphasis adjust bit 3 (msb) preemphasis setting: peadj2 preemphasis adjust bit 2 preemphasis (db) register setting peadj1 preemphasis adjust bit 1 0 0000 peadj0 preemphasis adjust bit 0 (lsb) 1 0001 2 0011 3 0100 4 0101 5 0111 6 1100 7 1101 8 1111 amp1 output amplitude adjustment bit 1 output amplitude adjustment: amp0 output amplitude adjustment bit 0 00 = 350 mv pp 01 = 650 mv pp 10 = 650 mv pp 11 = 850 mv pp rsasel register rsa select bit 7 (msb) rate selection register a ? rsasel = 1 ? content of register a bits 3 to 0 is used to select the input filter bw ? rsasel = 0 rsa3 rate select register a bit 3 default bw of 2.4 ghz is used rsa2 rate select register a bit 2 rsa1 rate select register a bit 1 register rsa is used when rate1 = 0 and rate0 = 0 rsa0 rate select register a bit 0 (lsb) rsbsel register rsb select bit 7 (msb) rate selection register b ? rsbsel = 1 ? content of register b bits 3 to 0 is used to select the input filter bw ? rsbsel = 0 rsb3 rate select register b bit 3 default bw of 7.6 ghz is used rsb2 rate select register b bit 2 rsb1 rate select register b bit 1 register rsb is used when rate1 = 0 and rate0 = 1 rsb0 rate select register b bit 0 (lsb)
16 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated table 19. register functionality (continued) symbol register bit function rscsel register rsc select bit 7 (msb) rate selection register c ? rscsel = 1 ? content of register c bits 3 to 0 is used to select the input filter bw ? rscsel = 0 rsc3 rate select register c bit 3 default bw of 8.4 ghz is used rsc2 rate select register c bit 2 rsc1 rate select register c bit 1 register rsc is used when rate1 = 1 and rate0 = 1 rsc0 rate select register c bit 0 (lsb) rsdsel register rsd select bit 7 (msb) rate selection register d ? rsdsel = 1 ? content of register d bits 3 to 0 is used to select the input filter bw ? rsdsel = 0 rsd3 rate select register d bit 3 default bw of 9.0 ghz is used rsd2 rate select register d bit 2 rsd1 rate select register d bit 1 register rsd is used when rate1 = 1 and rate0 = 0 or rate1 and rate0 are not connected rsd0 rate select register d bit 0 (lsb) losasel register losa select bit 7 (msb) los assert level register a losa6 los assert level register a bit 6 losasel = 1 losa5 los assert level register a bit 5 content of register a bits 6 to 0 is used to select the los assert level losa4 los assert level register a bit 4 minimum los assert level for 0000000 losa3 los assert level register a bit 3 maximum los assert level for 1111111 losa2 los assert level register a bit 2 losasel = 0 losa1 los assert level register a bit 1 default los assert level of 15 mv pp is used losa0 los assert level register a bit 0 (lsb) register losa is used when rate1 = 0 and rate0 = 0 losbsel register losb select bit 7 (msb) los assert level register b losb6 los assert level register b bit 6 losbsel = 1 losb5 los assert level register b bit 5 content of register b bits 6 to 0 is used to select the los assert level losb4 los assert level register b bit 4 minimum los assert level for 0000000 losb3 los assert level register b bit 3 maximum los assert level for 1111111 losb2 los assert level register b bit 2 losbsel = 0 losb1 los assert level register b bit 1 default los assert level of 18 mv pp is used losb0 los assert level register b bit 0 (lsb) register losb is used when rate1 = 0 and rate0 = 1 loscsel register losc select bit 7 (msb) los assert level register c losc6 los assert level register c bit 6 loscsel = 1 losc5 los assert level register c bit 5 content of register c bits 6 to 0 is used to select the los assert level losc4 los assert level register c bit 4 minimum los assert level for 0000000 losc3 los assert level register c bit 3 maximum los assert level for 1111111 losc2 los assert level register c bit 2 loscsel = 0 losc1 los assert level register c bit 1 default los assert level of 26 mv pp is used losc0 los assert level register c bit 0 (lsb) register losc is used when rate1 = 1 and rate0 = 1
17 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated table 19. register functionality (continued) symbol register bit function losdsel register losd select bit 7 (msb) los assert level register d losd6 los assert level register d bit 6 losdsel = 1 losd5 los assert level register d bit 5 content of register d bits 6 to 0 is used to select the los assert level losd4 los assert level register d bit 4 minimum los assert level for 0000000 losd3 los assert level register d bit 3 maximum los assert level for 1111111 losd2 los assert level register d bit 2 losdsel = 0 losd1 los assert level register d bit 1 default los assert level of 26 mv pp is used losd0 los assert level register d bit 0 (lsb) register losd is used when rate1 = 1 and rate0 = 0 selrate3 selected rate setting bit 3 selected rate setting (read only) selrate2 selected rate setting bit 2 selrate1 selected rate setting bit 1 selrate0 selected rate setting bit 0 sellos6 selected los assert level bit 6 (msb) selected los assert level (read only) sellos5 selected los assert level bit 5 sellos4 selected los assert level bit 4 sellos3 selected los assert level bit 3 sellos2 selected los assert level bit 2 sellos1 selected los assert level bit 1 sellos0 selected los assert level bit 0 (lsb)
18 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information figure 15 shows a typical application with digital control. in this case din+ and din ? are connected to transimpedance amplifier (rosa) and dout+ and dout ? to sfp connector. sda and sck are connected to a microprocessor. 9.2 typical application figure 15 shows a typical application circuit using the onet8501pb. figure 15. typical application circuit 9.2.1 design requirements for this design example, use the parameters listed in table 20 as the input parameters. table 20. design parameters parameter example value supply voltage 3.3 v v in 20 mv pp to 2000 mv pp data rate 8.5 gbps to 10.3 gbps ac capacitors 0.1 f coc capacitor 330 pf disable vcc din+ din- dout- dout+ los dindin dout- dout+ vccvcc gndgnd onet 8501pb 16 pin qfn c1 0.1 mf c2 0.1 mf c5 330 pf c60.1 mf c4 0.1 mf c3 0.1 mf l1 blm15hd102sn1 coc1 coc2 dis los sda sck rate0 rate1 sda sck rate0 rate1 copyright ? 2016, texas instruments incorporated
19 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 9.2.2 detailed design procedure the purpose of the series resistors is to improve the signal integrity between the vcsel driver and the vcsel. because the vcsel impedance varies depending on its type, the series resistor provides a better matching impedance for the modulation current outputs. the output amplitude adjustments are set as: amp0 = 1 and amp1 = 0 (see register 3 ). din+, din ? , dout+, and dout ? are ac-coupled with 0.1 f. 9.2.3 application curves figure 16. output eye-diagram at 10.3 gbps vs and input voltage (20 mv pp ) figure 17. output eye-diagram at 10.3 gbps vs and maximum input voltage (2000 mv pp ) figure 18. output eye-diagram at 8.5 gbps and input voltage (20 mv pp ) figure 19. output eye-diagram at 8.5 gbps and maximum input voltage (2000 mv pp ) 100 mv/div 20 ps/div 100 mv/div 20 ps/div 100 mv/div 20 ps/div 100 mv/div 15 ps/div
20 onet8501pb slls910a ? july 2008 ? revised june 2016 www.ti.com product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 10 power supply recommendations the onet8401pb is designed to operate with an input supply voltage range from 2.95 v to 3.6 v. for sfp+ modules, the onet8501pb must be used because of its low ac common-mode voltage. the supply current of the onet8501pb is dependent upon the output amplitude setting. the typical setting for an sfp+ module is the 650-mv pp output voltage. the typical supply current in this case is 50 ma leading to 165 mw. 11 layout 11.1 layout guidelines for optimum performance, use 50- transmission lines (100- differential) for connecting the high-speed inputs and outputs. the length of transmission lines must be kept as short as possible to reduce loss and pattern- dependent jitter. ti recommends maximizing the separation of the dout+ and dout ? transmission lines from the din+ and din ? transmission lines to minimize transmitter to receiver crosstalk. 11.2 layout example figure 20. onet8501pb layout example ac-couplingcapacitors dout+doutC din+ dinC from rosa coc capacitor
21 onet8501pb www.ti.com slls910a ? july 2008 ? revised june 2016 product folder links: onet8501pb submit documentation feedback copyright ? 2008 ? 2016, texas instruments incorporated 12 device and documentation support 12.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.2 community resource the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.3 trademarks e2e is a trademark of texas instruments. all other trademarks are the property of their respective owners. 12.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 12.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples hpa00503rgtr active qfn rgt 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 100 85pb ONET8501PBRGTR active qfn rgt 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 100 85pb ONET8501PBRGTRg4 active qfn rgt 16 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 100 85pb onet8501pbrgtt active qfn rgt 16 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 100 85pb onet8501pbrgttg4 active qfn rgt 16 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 100 85pb (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device.
package option addendum www.ti.com 15-apr-2017 addendum-page 2 (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ONET8501PBRGTR qfn rgt 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 onet8501pbrgtt qfn rgt 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 onet8501pbrgtt qfn rgt 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 q2 package materials information www.ti.com 3-feb-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ONET8501PBRGTR qfn rgt 16 3000 367.0 367.0 35.0 onet8501pbrgtt qfn rgt 16 250 210.0 185.0 35.0 onet8501pbrgtt qfn rgt 16 250 210.0 185.0 35.0 package materials information www.ti.com 3-feb-2016 pack materials-page 2

www.ti.com package outline c 16x 0.30 0.18 1.68 0.07 16x 0.5 0.3 1 max (0.2) typ 0.05 0.00 12x 0.5 4x 1.5 a 3.1 2.9 b 3.1 2.9 vqfn - 1 mm max height rgt0016c plastic quad flatpack - no lead 4222419/b 11/2016 pin 1 index area 0.08 seating plane 1 4 9 12 5 8 16 13 (optional) pin 1 id 0.1 c a b 0.05 exposed thermal pad symm symm notes: 1. all linear dimensions are in millimeters. any dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. the package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. scale 3.600
www.ti.com example board layout 0.07 min all around 0.07 max all around 16x (0.24) 16x (0.6) ( 0.2) typ via 12x (0.5) (2.8) (2.8) (0.58) typ ( 1.68) (r0.05) all pad corners (0.58) typ vqfn - 1 mm max height rgt0016c plastic quad flatpack - no lead 4222419/b 11/2016 symm 1 4 5 8 9 12 13 16 symm land pattern example scale:20x notes: (continued) 4. this package is designed to be soldered to a thermal pad on the board. for more information, see texas instruments literature number slua271 (www.ti.com/lit/slua271). 5. vias are optional depending on application, refer to device data sheet. if any vias are implemented, refer to their locations shown on this view. it is recommended that vias under paste be filled, plugged or tented. solder mask opening metal under solder mask solder mask defined metal solder mask opening solder mask details non solder mask defined (preferred)
www.ti.com example stencil design 16x (0.6) 16x (0.24) 12x (0.5) (2.8) (2.8) ( 1.55) (r0.05) typ vqfn - 1 mm max height rgt0016c plastic quad flatpack - no lead 4222419/b 11/2016 notes: (continued) 6. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. symm all around metal solder paste example based on 0.125 mm thick stencil exposed pad 17: 85% printed solder coverage by area under package scale:25x symm 1 4 5 8 9 12 13 16 17

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