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Integrated Circuit Syst...
ICST[Integrated Circuit Systems]
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| Part No. |
ICS9DB102GLFT ICS9DB102 ICS9DB102FLFT
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| OCR Text |
...able for SRC/PCI Express output pair '0' 0 = enabled, 1 = tri-stated Power supply, nominal 3.3V Ground pin. True clock of differential PCI_Express pair. Complement clock of differential PCI_Express pair. Power supply, nominal 3.3V Data pin ... |
| Description |
2 Output PCI Express Buffer with CLKREQ Function
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| File Size |
124.26K /
10 Page |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS95V842
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| OCR Text |
...5V "True" Clock of differential pair output. "Complementary" Clock of differential pair output. Ground pin. "True" reference clock input. "Complementary" reference clock input. 3.3V Analog Power pin for Core PLL Analog Ground pin for Core P... |
| Description |
DDR Phase Lock Loop Clock Driver (60MHz - 220MHz)
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| File Size |
71.33K /
9 Page |
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it Online |
Download Datasheet |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5V994PFI IDT5V994 IDT5V994JI IDT5V994PFGI IDT5V994PFI8
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| OCR Text |
...ew outputs Low skew: 200ps same pair, 250ps all outputs Selectable positive or negative edge synchronization: Excellent for DSP applications Synchronous output enable Input frequency: 17.5MHz to 133MHz Output frequency: 17.5MHz to 133MHz 2x... |
| Description |
3.3V Programmable Skew PLL Clock Driver TurboClock Plus
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK-TM PLUS
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| File Size |
65.67K /
9 Page |
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it Online |
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ICST[Integrated Circuit Systems]
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| Part No. |
ICS8737AG-11T ICS8737-11 ICS8737AG-11
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| OCR Text |
...LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency up to 650MHz * Translat... |
| Description |
LOW SKEW ±1/±2 DIFFERENTIAL-TO- 3.3V LVPECL CLOCK GENERATOR
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| File Size |
93.34K /
13 Page |
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it Online |
Download Datasheet |
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Price and Availability
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